tri-state bus

[djkok]

I am newcomer for this forum.
By the way, I am really amaze with the professional engineer answer in the forum.

I face a proble on the tri-state bus definition.
Is anybody can help me to give more details explanation on the tri-state bus application.

What is the purpose using the tri-state desing in development a chipset IC.

really appreaciate your help

 

[VEBill]

Tri-state means three states - that's one more than the usual LOW and HIGH. The extra state is HI-Z (disconnected). Being disconnected allows other output devices to take control of the line (usually part of a bus).

Basically - you can't have one device driving the line LOW or HIGH and expect another device to fight with it. Tri-state allows multiple outputs to share a bus without fighting.

 

[Skogsgurra]

Yes, exactly. If you study popular bus buffers like the 74LS645 you will see an Enable signal (pin 19). That signal is ANDed with the direction signal and the resulting signal controls the buffer stages. A true signal activates the buffer stage and a false signal Tri-States it so that it does not disturb other signals on the bus.

An alternative would be to use open collector outputs. The 74LS641 is such a bus buffer. It needs a pull-up resistor on each line and it cannot be used in fast systems since the pull-up resistor cannot charge the bus lines fast enough (RC time constant too long).

 

[IRstuff]

While it might appear that open-collector and tri-state are comparable, the big difference is that open-collector can only be used with a passive pullup such as a resistor. This results in several issues:

>> Limits the amount of sourcing current, since the pulldowns must be capable of sinking that current.

>> Since the current is limited, the rising transients will be significantly slower than the falling transients

>> Since the load is always enabled, low signals will draw DC power, whereas a tri-state buffer will switch off its pulldown transistor during rising transients

TTFN

 

[automatic2]

so what this gives you is the ability to populate a 'data bus' with a number of buffers, all synchronized by a seperate control bus. One of the most common implementations is the multiplexed address/data bus of the intel 80x processors. All data buffers must tristate whilst the processor is outputting addressing info to the address latches. Another consideration is in phasing of digital propogation. Common in the Motorola 65xx processors where buss transfers where activated/floated in relation to clock phasing.

 

[maged541946]

There is another difference between Tri state and open collector.
If you disable an open collector, it defaults to Logic Hi due to resistor pull ups, and there is no way (without using a set of inverters) to default it to low, however when a tri-state is disabled it is high impedence which enables you to select any load pull up or down, this load is NOT like the pullup in the sence of slowing down buss because when buss is enabled its speed is set by the driver and device input (assuming shortest connections)
For the same reason, if there is a posibility that all outs are tri stated at a time, never leave the input that they feed go floating, as any kind of faults may be expected then.


Maged A. Mohamed

http://magedm.freeyellow.com

http://www.magedsoft.com

 

[IRstuff]

Open-collector, by definition, is NEVER disabled. It is a wired-OR function at ALL times.

TTFN

 

[VEBill]

If you invert the logic (1<>0), it can be wired-AND too.

;-) !!

 

[IRstuff]

Sorry, my bad De-Morgan's, should have been wired NOR

TTFN

 

[lcsjk]

A tri state output has one transistor to pull the output to ground and another transistor to pull the output to VCC. Only one of these transistors will be on at any one time so that the output is either high or low. Although only one can be on at any time, they can both be off at the same time. When the output is not pulled up and not pulled down either, it is said to be in tri-state mode. At that point, the output wire is electrically disconnected, floating. If there is some other tristate device connected to the wire, it can take over and control the output. Two or more tri-state outputs can connect to the same wire in parallel as long at one is set to the tri-state mode.

 

[maged541946]

wire OR is when 2 or more Open Collectors are active in the same time on a wire or buss, without enable you can not expand memory chips for instance...

In T.I. TTL data book the 74/54 TTL series, they have data sheets for the following ( 74L LS and S are ommitted from part number)

440 Non Inverting quad Tri Direction buss transiever.
441 Inverting quad Tri Direction buss transiever.
471 Inverting and Non Inverting buss transiever.

471,473,475 are all PROM's
289 is a 16x4 RAM
301 is a 256x1 RAM
186 and 187 is a 64x8 ROM
270 and 271 ROM

170 is 4x4 register file
156 Decoder Demultiplixer
159 4 to 16 line decoder demultiplier

All the above have chip select and or enable for expantion.
Some other manufacturers in Europe made some other seires (not 74/75) and TTL compatable and use Open collector tech.

Same tech is found in few CMOS chips and called open drain too.
Best regards

Maged A. Mohamed

http://magedm.freeyellow.com

http://www.magedsoft.com