Voltage Reference Divider

[Noway2]

I have been looking at ADC chips, and it appears that a lot of them can accept differential or pseudo differential signals that are centered about Vref / 2.

What I have been trying to figure out, is what would be the best method to generate the one half voltage reference. While it would be possible to use two reference sources, the tolerances could go in opposite directions, which would be less than ideal. If, however, one had a reference and one that was exactly 1/2 of it, at least one form of error could be removed.

The problem I see with using a resistor divider is that even with .1% resistors the result is only accurate to .2% which is about 5x worse than the voltage reference, which is .04% or about 2 LSB. I did see that Maxim makes a form of matched eepot with four resistors, which they call a precision attenuator and the claim that it is accurate to .025%.

I also searched for matched resistors, R2R ladders and all the varients of these terms that I could think of trying to find a resistor network that had a matched accuracy, pretty much to no avail.

I was wondering if anyone has had experience designing this type of reference voltage and if so, what would you suggest?

One possibility I have considered, is to use a resistor divider with an eepot connected by a large resistor and then tweaking the eepot to bring the converted output to half scale. This is a technique I used in the first prototype, and it worked satisfactorilly, but I wonder if there is a better alternative.

 

[cbarn24050]

1 common way is to use an op amp, use a trimmer to ajust the voltage to the required accuracy.

 

[Noway2]

While that would work and is relatively inexpensive, I failed to mention that I would like a method that can be automated by the controller. There are two reasons for this. First, the product will go into environments that can have a fairly wide temperature variance over time so adjustments may need to be performed periodically for maximum accuracy. Second, based on past experience with this type of action on other products, I don't believe that I can count on the labor force to setup or test the hardware correctly.

 

[benta]

If you are giving the ADC differential input, I don't see why the Vref/2 should be specially accurate. The only point where it's relevant is at the extreme ends of range, where an inaccurate Vref/2 would cause the input voltage to exceed common mode range. But in that case, your design would be marginal.

Benta.

 

[sreid]

I think that most of the A/Ds have a Vref/2 pin that can,say, be buffered with a precision opamp that can be used as the offset for the input buffer amplifiers. Any Vref drifts then track with time and temperature.

 

[itsmoked]

The standard way to get your voltage divider for that use is to use a resister network. Even the cheapest crummy networks work exceedingly well. They are even spect'd that way.

They contain a bunch of resistors that all drift IDENTICALLY because they are all built on the same substrate. It doesn't even matter (within reason) what the values are because they will always be the same ratio as the temperature of the ambient changes.

Surface mount or thru hole.

http://www.bourns.com/components.aspx?cmsphid=7631383|7163299|3711038#tkf

If you need more current then you run the divided voltage thru a LTC2054 (zero drift opamp).

 

[logbook]

itsmoked,

I am offended on principal that you would use the term IDENTICAL when refering to analog stuff. What you mean is that the resistors on the same substrate "track" so that a 100ppm/degC absolute TC might translate into a 5ppm/degC tracking TC for example. The tracking TC is not ZERO!

Some people might refer to the tracking TC as the ratio TC.

 

[Noway2]

First, I would like to thank everybody for their suggestions. Not only does the feedback help me improve the design I am working on but I am also learning more about the Artistic side of electronic design.

The ADC that I am thinking of using has an internal voltage reference of 2.5V but has a bad (20ppm) temperature co-effecient, but the reference pin can be overdriven by an external reference if better performance is desired. My game plan is to first use a better reference, second my signal measurements will be made in reference to (analog) common which will connect to the AN- input, third use an offset of 1/2 of the refence as a zero input which is also used to bias the input amplifier stages, i.e. no input provides Vref/2 signal to the ADC for 0 in twos complement output from the converter. The desire to offset the signals to half reference is to provide the ability to monitor both positive and negative signals and also to bias small signals away from the bottom of the conversion range.

I am going to tread on sacred groung here, so my appologies in advance. My normal inclination, as far as unified versus seperate analog and digital grounds is that one ground works best but carefull layout procedures help ensure that digital logic doesn't contaminate the analog areas. As Warpspeed said in another post, the system has the potential of seeing negative DC swings on the ground and as a result, my battery power(s) and ground(s) are diode steared (to generate the digital logic power). The diodes on the ground side, which I suspect are necessary, make it difficult to use a totally unified ground. In this case, my analog measurements will be made with respect to the analog common, which is the sensor common which is the system chassis. Unless I am totaly missing something, which wouldn't be the first time, the power circuitry should keep the analog ground clamped to within a diode drop of the digital ground. Consequently, my analog readings will be made with respect to the system chassis ground, and digital ground, which would could be susceptible to ground swings in catestrophic fashion should be safe due to the clamping. Since the sensors are crappy automotive type resistive sensors, I am planning on measuring the diode steared battery hot voltage, which I am supplying was a the signal reference (relative to analog common). This way, I can read the sensor as a percentage of the reference and the absolute tollerance of the sensor resistor shouldn't matter. Also, since the sensors are potentially chassis grounded at the sensor, using seperate analog and digital grounds prevents ground loops that otherwise would be difficult to avoid.

Back to the reference divider....

For the reference, I was thinking along the lines of a resistor network, specifically an R2R ladder, but I was having trouble finding parts when I searched on Digikey. I suspect I should look for another supplier as it doesn't appear that they are carrying much in the realm of SMT resistor networks anyway.

itsmoked, according to your post and the link, it seems like the manufacturing process is such that say a 1k resistor network may be off 5%, but that each resistor is going to be off by the same amount. If this is true a cheap network would work fine. If, however, one resistor is 950 Ohms and the next one is 1050 ohms, that would be a problem. This was my thinking too, that devices on the same substrate would have the same temperature and hence vary linearly. This is what I was looking for when I was searching for terms such as matched resistors.

 

[buzzp]

You can also measure the reference signal when a measurement is taken. Then temp variations don't matter. Of course, another channel would be required but would give the most accurate reading. Or you could mux them.
If the tolerance of Vref/2 is such to cause some peaks and valleys to be cut off, then you better scale the measured signal a little better.

 

[nbucska]

The simplest would be to switch the input of a lowpass
filter with an analog switch [AS] between GND and Vref with
50% duty cycle. Select an [AS} with negligeable
on/off time difference and other errors

<nbucska@pc33peripherals.com> omit 33 Use subj: ENG-TIPS
Plesae read FAQ240-1032

 

[itsmoked]

logbook; point taken.. too much literary license..

Noway2; you need to check the literature but generally we never saw those kinds of variation between values in the same package.

I would never diode isolate the ground side of a system. Any potential gains are offset by the many detractions that come from it. (((shudder)))

Just one example: what if you have an AC noise dumped onto the A/D board? Now you might have a halfwave rectified noise that gets your A/D board galloping along... Yuck.

nbucska; I don't know if I would call that "the simplest" method but it is certainly a good one also! I have used it several times to good effect.

Noway2; Too-wit look at the first application (down in the applications part of the data sheet) I have used this form often.

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1010,C1203,P1248,D3572

Excerpted here as:

 

[nbucska]

Smoked:
well, try to match the predictability and ease of design of the PWM DC voltage divider with resistive divider without adjustment...



<nbucska@pc33peripherals.com> omit 33 Use subj: ENG-TIPS
Plesae read FAQ240-1032

 

[logbook]

Noway2,

this thread seems to be wandering all over the place. Initially you had a differential input and were trying to create an accurate VREF/2 signal to bias it. Benta correctly stated that this would be a common-mode signal and the ADC would reject it. A 10% accuracy on the centre point would have been accurate in this case. It now seems as if you are using a non-differential input and you want a zero input into your front end amps to give EXACTLY mid-scale output from the ADC.

This requirement is unusually difficult and is not a sound way of designing the system. You will need to use incredible accuracy in all parts and frankly with a CMOS ADC I doubt you will make it. The normal technique is to do an automatic zero calibration. The easiest method is to manually or electronically short the input to the front end amp and measure the ADC value. The digits define this as zero and subtract it digitally from all readings. Remember that I am an analog designer (20+ years) but stuff like this is best done digitally. The next method is to short the input as before but use a digital offset control to bring the output to the desired midrange value. This method is slower and iterative but does optimise the symmetry of the ADC in terms of plus and minus deviations.