biasing a mosfet or heating issue

[jimmylovesni]

Hello,
I am having trouble with the power consumption by a paired mosfet array chip. The should be simple circuit is attached. The mosfet array (half bridge chip – FMP26 by IXYS) is being switched at 1-2MHz and thus, a 12A pin driver (EL7158) is being used to deliverer more current to the larger gate capacitance at the high frequencies (under 500khz the pin driver is not needed). So this is a high current, 10V output square wave of around 1Mhz used to drive each of the mosfet gates.

As I gradually increase the voltage on the P channel source up to 50-60V, the mosfet gradually gets hot, and this is without a load on it.. Now this effect is reduced by lowering the resistor (100 ohm in attached figure) value which is biasing the gate, reduces VGS by creating DC offset on the gate which lifts the pulse waveform. Im not sure what is going on though and how to properly bias this as 100 ohms is very low. Shouldn’t I be able to switch it with these VGS or whatelse is the problem

Mosfet datasheet

http://ixdev.ixys.com/DataSheet/DS100033A(FMP26-02P).pdf

circuit diagram

http://files.engineering.com/getfile.aspx?folder=980ce9ab-c909-48ad-99f7-b8252fb6ee67&file=fmp26.bmp

oscilloscope waveform 60V

http://files.engineering.com/getfil...638882e231&file=IMG_20110609_182149_small.jpg

many thanks
jim

 

[VEBill]

Maybe there's a bit of overlap causing little dead shorts from rail to ground. Can you monitor the current from the 60 or 70 volt rail and watch for sharp current pulses (again with no load)?

The fact that you report heat with no load sounds suspicious. Unless the gate drive itself is causing heat (?).

PS: your scope is from the future... ;-) 10-Jun-11

 

[ScottI2R]

I had a similar problem back when I first became a member here. I "upgraded" from an IRF 340 to a IRF 460 and neglected to take into account the increased gate capacitance. Started cooking IRF 460's. Well, the fine professionals here clued me in on the errors of my ways and I calculated the difference and reduced Rg accordingly. Never smoked another one. I would look at reducing your gate resistor. Look what they are using on the datasheet...

Scott

I really am a good egg, I'm just a little scrambled!

 

[BrianG]

The 'scope waveform shows the problem: it's clearly not switching cleanly as evidenced by all that oscillation on the back edge which will cause lots of heating. To me this indicates one of two causes: either there is an overlap where both devices are partially 'on' together or one device is going into spurious oscillation.
To prevent an overlap you may need to try different value gate resistors for the P and the N channnel devices instead of both being 100 ohms (see data sheet). This can help offset the differences in turn-on and turn-off times between the two device types. To reduce spurious oscillations a small resistor in series with each gate e.g. 1 or 2 ohms may help.

 

[electricuwe]

I'm only seeing some nasty electrolytics (for the 10 V as well as for the 10..70 V)decoupling the supplies.

Try to connect some ceramic capacitors using a low inductance layout technigue.

You have to regard such circuit as Rf-circuit although it's "only" 1 MHz.

 

[vangjer]

I'm just curious, what kind of application are you building this circuit for?

 

[sreid]

1) From the circuit schematic, it looks to me that the On gate drive is 5 V. The gate turn on threshold is speced at 2.5 to 5 V.

2) Overlap of the FET turn on / turn off delays can cause both FETs to conduct briefly. Some delay must be added between turn on and turn off.

 

[zappedagain]

What is the source resistance of your driver? Without resistance in series with your gate the lead inductance on the source will cause wild oscillations that will look like ringing, pretty much what your scope photo shows.

Z

 

[LionelHutz]

I would also suspect a dead-time issue. I have typically seen that type of configuration with 2 gate drive circuits with a minimum dead-time between them.

You also need a resistor in series with each gate too. The data sheet says 3.3ohms for the N-channel and 10ohms for the P-channel.

I too, would expect to see a 5V gate drive, which would actually mean +5V to -5V. The 0.1uF gate caps will charge to some DC value in operation. I would expect this to be 5V but it could easily end up as some other value.

 

[vangjer]

LionelHutz,

I also thought that it's a dead-time as well. It's possible that there's a shoot through. I had this problem on my buck converter, the high side transistor gets extremely hot under no load.

 

[iop95]

I think it's a deadtime problem. Low side T begin to conduct before high side T be full closed. So, for some time, even high side T begin to close and voltage on it increase, current also increase (because low side T conduct) instead to decrease ; in these conditions Pd = Vds x Id is high and temperature increase. I think decreasing resitor value of low side to 65-75ohms will increase deadtime.

 

[electricuwe]

To sreid:

How do you come to conclusion 1) ?