Calculated Gap Between Internal and External FOS with TOP

[EveTrujillo]

Hi Guys,
I'm confuse with how calculated the gap between to mating FOS controlled with TOP, in we have a hole and a pin, what is the value of the gap or the interference between this 2 FOS?? Please see the attached file..

thanks
EveTrujillo

 

[Woosang]

Assumed the hole and the pin are nominally coaxial.

Minimum gap is when both hole and pin are in their virtual condition, since virtual condition is maximum material boundary that shall not be violated considering feature's MMC size and maximum allowed position tolerance.

Thus, Min Gap = (31.2-3.7)/2 = 13.75

Maximum gap would be when both hole and pin are at LMC, in addition, considered that axis of hole and pin are displaced in opposite direction by the amount of maximum allowed position error,as shown in below figure.

Thus, Max Gap = A-B = (31.9/2+0.35)- (3.4/2-0.15)= 14.75

There might be some other nice and simple calculation, which doesn't cross my mind now.

 

[pmarc]

Woosang's calculations will work under one condition - both FOS in question, internal and external, have to be located relative to datums that in assembly get perfectly aligned with each other and no shift/movement between them is possible. In other words, if two parts, one with the hole and second with the pin, mate with each other such that a loose between them is possible, the amount of that loose has to be taken into account in the calculations of min and max gap between the pin and hole.

 

[EveTrujillo]

Thanks guys, for you support...
the image was a big support too.
so, the minimum gap = Int VC/2 - Ext VC/2
the max gap = Interal RCB/2 - RCB/2

so, if I add a datum shift, the maximum and the minimum gap is calculated different?