Could a PLL do the job ? 1

[walker1]

We have a mechanical device for one of our IR cameras that is rotating a disc in front of the lens.

There is a 40/60% (approx.) duty-cycle signal coming out of the thing (1 pulse pr. rev.) and another that gives two short pulses pr. rev.

The one pulse pr. rev. has a problem, however. At times we have x-tra pulses, or the pulse is delayed 1/2 rev.
The errors usually happen at random with several seconds interval, which coresponds to something like 1% of the pulses.

We want to use this one pulse pr. rev. signal to synchronize our framegrabbing, so we need to correct the signal somehow.

I have thought about creating a PLL by using a 74HC4046, thus creating my own copy of the signal, and use the partly bad signal for keeping it fairly synchronized.
With a slow enough loop filter, the errors should have little enough influence to make it work, or ?

Other ideas ?


The vendor (DIOP, from New Hampshire) has been told about this, but they have received their money long ago and couldn't care less, it seems. We have no documentation on what goes on inside, but I guess it has to do with an internal latch delay or something. Possibly inside a PLD.

 

[Skogsgurra]

It will work wonderfully. You may have some phasing problems, but nothing that can't be corrected with either an external filter or by adjusting the detector output DC level by injecting a +/- signal. There will, of course, also be some time needed for the PLL to lock onto the signal.

The next best thing seems to be a little micro that "learns" the timing and keeps it so to bridge occasional dropouts.

Another rather crude technique would be to use a huge LC resonant circuit. But I wouldn't recommend it.

 

[melone]

Where is this extra pulse coming from? I am just afraid that masking the problem won't give you the best results.

 

[nbucska]

The encoder supplies two signals : the CLK and INDEX.
Use a double PLL --one for each. Reclock the INDEX
with the phase of the CLK.PLL which leaves the larger
margin.



<nbucska@pcperipherals.com>

 

[felixc]

Depending on what the error pulses are, you may want to try a monostable circuit to disable any further pulses from going through during say 80% of the rotation time after a first pulse is detected. This would keep a valid time window around where your pulse should be. It is a simple circuit, easy to try.

Felix

 

[Skogsgurra]

felix,

That is a radiant example of &quot;thinking outside the box&quot; and KISS. You get a star for that.

 

[walker1]

The idea from felixc is quite clever. Unfortunately it will onlý remove the instances where I have three pulses in a row (once every 1/2 cycle), which is about 50% of the error cases.
(I currently have no idea how this happens)

In the rest of the cases the pulse seems to simply be delayed 1/2 cycle. (Some internal latch setup delay error is my current guess)
The following pulse in these cases comes 1/2 cycle later and are thus back on track.

I don't think we can live with missing an entire cycle now and then.
Otherwise one could use an extended version of felixc's idea to create a qualifier inside which, a pulse will be accepted.

In our case the one-shots will have to be counter/timer based, however, as the rotation frequency can be adjusted from 5 to 170 Hz.
(We do have a number of counter/timers available

 

[nbucska]

you can do the pll with timers, too.

<nbucska@pcperipherals.com>

 

[felixc]

This is what I meant with the use of monostable, using the idea to bring a time window of interest for the next valid pulses. If the rotation frequency of your device varies that much, you will have hard times with a PLL. Using counter/timers to create that window of interest is probably your best bet. Have fun!
Felix

 

[melone]

Instead of masking the "bad" pulses, why don't you figure out why they are being generated? Perhaps, the pulse generating unit is bad?

 

[Heydave]

I did a circuit like this to avoid impulse noise on a digital telephone. I ran a 4046 PLL at a multiple of the primary pulse rate and used the feedback divide counter states to open and close a sampling window to maintain a frequency lock. Errors that made a pulse early or late were limited to the window width. This resulted in a very stable lock that was immune to most glitches. The states of the counter could be used to enable a trigger for your error capture. From my experience, the 4046 is good for about a 2 to 1 frequency range to be stable. The entire circuit could be implemented using a digital PLL running off a high frequency clock but keep in mind that it will jitter according to the pulse width of the master clock. The master clock of a digital PLL does not need to be a multiple of the pulse you are trying to sync.