Externally summed CTs for bus protection 3

[Mbrooke]

Starting this not to steer off another thread, but I inquire 2 questions:

1. At what point or fault levels do engineers typically move away from externally summed CTs for (over-current) bus differential protection? C800 class CTs of concern here FWIW.

2. Can externally summed bus protection CTs be used in networked circuits?

 

[davidbeach]

About a decade ago... ;-)

There's at least a couple of way of interpreting that question. If you're using an overcurrent relay as a bus differential, everything is summed external to the relay, so that may not really be what the question is.

If you're talking a differential relay that produces restraint and operate currents, either electrically or numerically, you have to be careful what you sum up externally. You need to have every source on its own CT but you can parallel up loads. The problem with paralleling a source and a load is that for an external fault on that load circuit your restraint current will be much lower than it would be if every CT had its own input. Throw in a bit of error, and that missing restraint current may be allow the relay to operate for an external fault.

 

[Mbrooke]

Basically using an over current relay (351) for bus protection vs using a B90 or 487B. The over current approach is much simpler and I've seen it used extensively on distribution buses- but I am wondering at what point it begins to have its limitations.

 

[davidbeach]

That's essentially a low impedance version of the high impedance bus diff. For my liking, we still have far too of them. But for that application all CTs are summed external to the relay, so I'm not sure what the original question is asking. If it's all currents summed into an overcurrent relay vs. a low impedance bus diff I'll stick with my original answer of about a decade ago. It's not something I'd even consider today.

 

[Mbrooke]

But why the choice of a low impedance bus differential relay over an over-current relay? Why the switch? My apologies for not being clear about this in the first post.

 

[davidbeach]

If the choice is a low cost EM overcurrent vs. a higher cost EM differential and there aren't going to be performance issues then the EM overcurrent makes sense, in that environment. Those were the "well, it reclosed, everything's ok" days. Now we have a compliance obligation to know that every operation is correct. There's also been a transition from (before my time) where stuff seemed to be expensive and personnel time inexpensive to where stuff is less expensive and personnel time is more expensive. So if a more expensive relay requires less time figure out what happened that's a good thing.

That may be a bit simplified, but 20 years ago we'd pick just the "right" relay for the application and have lots of different relays to purchase, design around, and maintain spares for. Now it's believe to be less costly to have as few different designs as possible and some applications get a design that would have been considered gross overkill 20 years ago. Part of it is compliance obligations, part of it is simply trying to get more out of each protection engineer than 20 years ago and there's no time to "optimize" each design, nor do we see the point.

I'd much prefer to get really good at a handful of standard designs, portions of which may be omitted at any given location, than to come up with just the right design every time.

So, if I need a full out low impedance bus diff design I see absolutely no value in also having an overcurrent based design. Would an overcurrent relay work some places? Sure, undoubtedly; but the savings would be illusionary.

 

[stevenal]

If by externally summed, you mean connecting the CTs in summation external to a current relay; the problem is the lack of restraint for through faults. The answer then is: when you don't want to trip for through faults, use a multiple input, muti-restraint low impedance bus differential relay. The other option is to use a high impedance relay.

 

[HamburgerHelper]

I am replacing a mechanical high impedance relay with a low impedance microprocessor in a project I am currently working on. The comment was that I was given to not worry about CT saturation for external faults was that SEL's CT saturation restraint algorithm will prevent external fault tripping. I am not sure what to say about that. For event analysis, it is nice to see all the currents but I don't know how much I should be trusting an algorithm for blocking out of zone tripping. If we just used a high impedance diff relay, we wouldn't have to rely on an algorithm to prevent out of zone tripping. The high imp relay would guard it by design.

 

[Mbrooke]

@David: But nothing beats the elegance of simplicity In my case it will simply be two more feeder over current relays. The 487b will actually be a departure from the feeder relays. Although I do agree and very well put as per usual. However, I am also looking at this from an electrical theory perspective related to performance. I've been told that one of the down sides to over current buss differential is that when a feeder faults, the faulted feeder CT is far more likely saturate and inadvertently trip, however I do not know to what extent or what fault current levels this is more likely to happen? My understanding is that all low impedance designs are prone to saturation, just one handles it with logic. Or am I wrong?

 

[Mbrooke]

I am replacing a mechanical high impedance relay with a low impedance microprocessor in a project I am currently working on. The comment was that I was given to not worry about CT saturation for external faults was that SEL's CT saturation restraint algorithm will prevent external fault tripping. I am not sure what to say about that. For event analysis, it is nice to see all the currents but I don't know how much I should be trusting an algorithm for blocking out of zone tripping. If we just used a high impedance diff relay, we wouldn't have to rely on an algorithm to prevent out of zone tripping. The high imp relay would guard it by design.

Being SEL I am sure you will get your moneys worth. Unless you are dealing with profound saturation the relay should restrain on external faults but trip immediately on internal ones. However, FWIW I do know of utilities that have modernized their relaying from EM to microprocessor but kept the high impedance bus protection. Here is one example of a paper by SEL where a utility actually chooses electromechanical relays for bus protection despite replacing everything else. See page 10, descriptions numbered 2 and 7:

https://cdn.selinc.com/assets/Liter...Control_DA_20041019_Web.pdf?v=20170327-062930

 

[cranky108]

Not knowing the application, and assuming it might be in switchgear, high speed might be of a concern. In that case, an over current might be too slow.

There are papers on the advantages of both low and high impedance relays, and the answer is it depends on you, your application, your people who work on it, etc.

 

[Mbrooke]

No gear, just outdoor bus work.

 

[stevenal]

When a CT saturates, it produces less than the ratio current; so overcurrent tripping is less likely not more. False differential operate current can result, but you'll be restrained by the quantities from the other feeders. The slope is set-able by the user. Work through the instruction book example to see if saturation is a concern.

 

[Mbrooke]

Which instruction book though?

My understanding is that when a CT produces less current, there is less current to cancel out the current coming from all of the other feeders combined. Ie, if bays 1-9 produce 90 amps and the saturated bay CT only produces 80 from saturation, 10 amps will flow through the relay when in theory it would be close to zero for a none saturated CT.

 

[cranky108]

One of the advantages of the high impedance differential is that the other CT's will force current through a saturating CT, instead of the high impedance associated with the relay.

If you expect that under some cases you will see error current, that should be taken into account in your calculations, such as slope or setting.

 

[stevenal]

Mbrooke,

I see SEL is now referencing IEEE C37.110. See the CT Requirements section of the 487B-1 manual. Looks like they may have a program available as well.

Your understanding is correct. With a low impedance relay, all currents flow into the relay and the differential current is summed in the relay. The input currents are used for restraint. As cranky said, you can set your slope (Iop/Irt) to allow for the 10 amps of Iop in your example.

 

[Mbrooke]

@stevenal thank you and I will check that out.

But what should I consider in setting if I do not have restraint current?

 

[stevenal]

I suppose you may be able to simulate your system and CTs so you could find a suitable pickup setting, but it is not an approach I would recommend. If you wish to parallel CTs, suggest going high impedance.

 

[Mbrooke]

So basically the recommendation from the most experienced is either a high impedance relay (587Z) or a numerically summed low impedance relay (487B).


Question. In places where saturation is unlikely (such as a distribution bus with 1200/5 C800 CTs 10,000amp and under short circuit) is over current differential protection still ill advised?

 

[jghrist]

Question. In places where saturation is unlikely (such as a distribution bus with 1200/5 C800 CTs 10,000amp and under short circuit) is over current differential protection still ill advised?

You need to look at the burden and the system X/R ratio as well as the fault current to determine saturation.
Vs = (1+X/R)·If·Zb
I would recommend low impedance with restraint or high impedance. If you are concerned about cost, consider a fast-bus trip scheme instead of bus differential. If you have microprocessor relays on the main, bus tie, and feeders, you might achieve 3 cycle operation without any additional relays or CTs.