generating a 32Mhz clock

[puthumbaka]

Hi,
I am trying to build a 32MHz clock signal from a ring oscillator circuit. I used 74HC04 CMOS inverters [five of them] but the maximum frequency i could get was only 20Mhz. I reduced the number of inverters to 3, but i could get only 23MHz. I found the 74HC04 was rated to operate for 75MHz. My guess is that the Tr and Tf for the inverter [6ns] are too high.
Could anyone suggest me on this? I want to build the circuit from simple components [without using VCOs and frequency doubling circuits]. I would appreciate any help and advice in this matter.
thanks.

 

[blcpro]

Is there a reason why you wouldn't just use a 32MHz oscillator?

 

[puthumbaka]

There is no obvious reason why I do not use an oscillator. Its just that I cannot figure out why the 74HC04 ring oscillator configuration does not work.

 

[Heydave]

The frequency that the device can toggle is not directly related to the delay through the device. The ring oscillator is based more on delay. Consider sending data in a radio signal bounced off the moon. You could send the data at extremely rates but don't expect it to get back quickly even though the data rate may be very high.
As for your circuit, you could also have delays caused by stray capacitance forming an RC delay with the output resistance of the previous stage. If I am not mistaken, most 74HC04 devices actually have several stanges internally with the final stage being a buffer. To drive this buffer, two input stages are needed thus three inverters. A five stage ring is actually 15 stages!

 

[IRstuff]

The issue with ring oscillators, particularly short ones, is that the gates never completely transition to an OFF or ON state, which means that the push-pull stages of the 74HC04 have both transistors on. This drastically alters the delay-time, since the current that would have been used for charging the next stage is being dumped in the push-pull itself.

That's why most ring oscillators used to measure propagation delay are generally built with dozens of stages to ensure that sufficient settling of the gates has occurred before the next transition shows up.

TTFN