How to model simple level shifter circuit

[joshxdr]

I am building a level shifter circuit for digital signals. It is part of a digital circuit test system. Input signal comes in by coax cable to a pair of 0.1" header pins using z-trace connector. Output signal is also uses coax cable connected to a pair of 0.1" header pins with z-trace connector. My level shifter falling-to-falling delay must match rising-to-rising delay. I am using an On Semi MC100EPT25 to convert my 3.2-4.0v input to a 5-8.3v output. The datasheet indicates very strong pulldown and weak pullup. If I connect this directly to my output headers, will I get slow rising edge? Should I use a pair of inverters between the level shifter and the output headers? There is no SPICE model for this part. Is there any way to simulate how this output might look?

 

[IRstuff]

"If I connect this directly to my output headers, will I get slow rising edge?"

Doesn't that depend on your REQUIREMENTS?


"There is no SPICE model for this part. Is there any way to simulate how this output might look? "

The datasheet tells you everything you need to know to do a simulation

TTFN

FAQ731-376

 

[joshxdr]

I would like the rising edge delay to match the falling edge delay within 2 ns. I would like to know if adding a buffer would make this better or worse.

 

[VEBill]

The datasheet for the MC100EPT25 indicates "24 mA TTL Outputs".

Coaxial cable is normally 50 ohms Zo. 5 volts peak into 50-ohm cable is 100 mA peak. 8.3 volts is worse at about 166 mA.

So **if the coaxial cable is long enough** (compared to frequency) to act as a 50-ohm transmission line, then this IC might have a very difficult time driving it.

 

[IRstuff]

Have you even read the datasheet? This part runs on a 3.3 V Vcc and already has a 0.5 ns delta in rise time, just on the part itself.

TTFN

FAQ731-376

 

[joshxdr]

The output of this device is NOT 24mA. I am shifting to 5 to 8.3v. My vee is 0 and my vss is 5v and vdd is 8.3. That is a 3.3v swing. If you actually read the datasheet, the Vol and Voh numbers show how assymetrical the drive is. The major source of parasitic cap in my circuit is the thru hole header pins. If someone knows a ballpark number for what that capacitance is I can plug that into pspice.

 

[joshxdr]

From the datasheet:

Table 5. TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; VEE = ?5.5 V to ?3.0 V; GND = 0.0 V; TA = ?40°C to 85°C
Symbol Characteristic Condition Min Typ Max Unit
VOH Output HIGH Voltage IOH = ?3.0 mA 2.2 V
VOL Output LOW Voltage IOL = 24 mA 0.5 V

For pulldown it can sink 24mA with only 0.5V shift of Vol off the rail. For pullup, sourcing just 3mA causes Voh to shift down 1.1V off the rail. 24mA TTL is a nice marketing ploy by On Semi but it does NOT reflect the actual capability of the part.

I found a document that says that a typical undrilled hollow via has capacitance ~1pF and inductance ~2nH. Maybe a through holw header pin would be about 10x these values?

 

[joshxdr]

I don't care if the level shifter has 1ns delay or 20ns delay. I can compensate for that with the calibration feature of my tester. I can't compensate for a delta between rising edge and falling edge. The delta is what I am trying to minimize.

 

[VEBill]

I'm still more curious about what exactly the circuit has to drive, besides the stray capacitance of the output header pins.

 

[joshxdr]

The signal travels from the level shifter to an IC being tested. CMOS input buffers. Sometimes through a probecard to a wafer. Sometimes to a packaged IC.

 

[VEBill]

You had mentioned coaxial cable on the output. Is it a specialized coaxial cable, or run-of-the-mill 50-ohm cable?

What length? Long enough to act as a transmission line at the bandwidths being discussed?

 

[joshxdr]

The coax cable is 1.5 meter 50ohm cable. The through-hole pins on the level translator will tend to filter out high frequency. There are similar bandwidth limiters on the DUT side (connectors and/or wafer probes). In theory it is possible to generate reflections, but using this kind of interconnect I am not sure they will be a big problem. There may be a bigger problem with LC resonance due to the parasitics.

 

[benta]

"It is part of a digital circuit test system."

For test systems, ICs exist for exactly this function. Search for ATE Pin Driver.

Benta.

 

[VEBill]

Joshxdr, you seem to be very concerned about the stray capacitance of the pins, etc. (you've mentioned it several times), but it *appears* that you're not understanding that you need to launch the pulse into a 50-ohm cable.

Apologes in advance if I'm making bad assumptions.

The point is that if you can design a driver circuit that can drive a 50-ohm cable with a sharp pulse (high bandwidth), then the stray capacitance of the pins is probably not something that would be a show-stopper. The proper approach is to do the best you can to match the impedance of the traces and pins to match the 50-ohm cable. That way these items just become part of the transmission line.

You've still not explicitly mention the bandwidth that you're operating at. But it would have to be fairly low to get to the point where you could ignore transmission line theory when driving a 1.5-meter long coax. Especially when you're so concerned about controlling pulse transition times.

 

[joshxdr]

Benta, thanks for the tip. I will look into ATE Pin Driver ICs. From a brief glance at one of the datasheets it looks like they require a serial interface and a lot of control signals, and they are designed for -1.5 to 6.0V operation. Not sure if this is the answer for this particular project, but it is good to know that it is available.

I am leaning toward adding a buffer and a 30ohm termination resistor after my level shifter. This should square up my edges and provide some protection from reflections. I don't want to fall on my sword to match impedences since the bandwidth of this system is somewhat low, but if I have the buffer there it is no problem to add a resistor.