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Integrator troubles in psu feedback loop

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Dryjoint

Electrical
Feb 2, 2005
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I've designed a psu for hot-wire cutting. Whilst it works very nearly as I wanted, I've never had much success with the integrator stage of feedback loops and this one was no exception. Quick description: The hot wire load is fed with phase-angle controlled ac from a transformer. The trigger for the triac is via an optoisolator fed by pulses from comparator U2/B. The BC184s are a zero crossing detector and the VN10/1uf cap supply a (falling) ramp waveform to the +ve i/p of U2/B so that as the voltage increases at the -ve i/p of U2/B, the trggering edge o/p is shifted from 180 to 0 degrees. Feedback is provided by sampling the voltage across the 0R22 in series with the load and cleaned up by the AD736 rms-dc converter. Anyone reading this far will probably see the error around U1/B, but try as I might, I cannot null the offset error, so I'm having to tailor the feedback gain to match a particular current range; not good. Any advice would help me retain some hair. Thanks.
 
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Match the impedence at the inverting and noninverting inputs at U1B by making the capacitor at U1B+ 220nf and the parallel combination of the 2 resistors at that node equal to 10K. Then use a lower value pot to set current. This will minimize your offsett problem.

The lower the value you can use for your current set pot the lower your offset will be. At some point there is going to be a trade off between offset and power you want to dissipate in the current set pot.




Dean Cooper
dclabseng.com
 
Thanks very much, Dean. So it's really that simple, eh? To keep the pot current low, I guess I could just put a buffer after it and the unmarked R & C, which are there for the option of pwm pulses from a pc to control the setpoint.
 
On second thoughts, that's way ott. A 100R pot is only going to dissipate 1/8 watt, and that's not allowing for the v drop in the opto. Maybe up the +5V reg to 1A version to be sure.
 
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