New to surface mount PCB's 5

[SteveSmith]

Hi,
I've done thru-hole PCB design for 25 years and am now
going to finally get to layout a surface mount design
for the 1st time. I'm looking for good reference data
on surface mount (books, magazine articles, etc.) and
any advice I can get. Thanks.

Steve Smith
Product Engineer
Staco Energy Products Co.

http://www.stacoenergy.com

 

[jbartos]

Suggestion: Subscribe for SMT Magazine at

http://www.smtmag.com

You may qualify for the free subscription. There is also more info available about SMT at that web site.

 

[Warpdrive]

Steve,

Some of the best reference data for pad sizes and clearances is to be found in the manufacturer data sheets for the parts specified in your design(s). These often have layout cell footprints typical of the packages surface mount parts come in.

Some general tips...

1. Advantage: Surface mount parts generally allow more routing flexibility in the PCB sandwich layers. Use it.
2. At some point, a surface mount connections may have to via to another layer.
3. Disadvantage: Surface mount parts are frequently smaller than thru-hole ones, with pad/trace size decreasing as circuit density increases. Wave soldering or oven soldering during assembly is required in most design cases. The design should be correct the first time, because rework is usually not feasible.
3A. TIP: Insert test points on key surface mount signals, routing them to some place accessible on the PCB.
4. The densest surface mount IC package today is the Ball Grid Array. Be extra careful on via size, pad diameter and via-pad clearances.
5. Do not place surface mount parts in areas where the PCB flexes. They can lose cohesion after enough flexing.

Enjoy.

Warpdrive

 

[SteveSmith]

Thank you both for the help.
I found the both informative. Steve Smith
Product Engineer
Staco Energy Products Co.

http://www.stacoenergy.com

 

[stelleb]

Steve, regardless of the data you may find in standard references and web sites, you may find as I have found several times now that the best pad size dimensions will come from the contract manufacturer that places and flows the board for you (they may actually be different). They will be able to tell you how much component to component/ testpoint/ fiducial/ spacing and count would best enable them to buil the board for you succesfully. Additionally, with the pitches getting finer and some contacts being hidden from us (i.e: BGAs) consider utilizing the JTAG features of the chips you have selected if possible. I garauntee it can make your board level testing both in prototype and production much easier.

stelleb

 

[SteveSmith]

Thanks stelleb,
I'm showing my ignorance here, but what is JTAG? Steve Smith
Product Engineer
Staco Energy Products Co.

http://www.stacoenergy.com

 

[stelleb]

Once the contacts in the case of a BGA become inaccessable to direct probing at the part, which is sometimes necessary to determine an open circuit condition, or even a short, the Joint Test Action Group got together and thought it would be nice if the designer still had access to as many nodes as possible. They implemented a simple shift register topology which basically placed an aditional bidirectional gate along side of existing pins in these parts. In some of the microprocessors I have worked with these shift registers have turned out to be any where from 100 to 800 bits long. These shift registers are controlled by a simple standard JTAG or IEEE 1149.1 state machine controlled by a minimum of 4 pins on the part. This allows the user to discretely exercise a pin on the part and see how the rest of the world sees the assertion. One example that I have used very effectively is examining for shorted nets, either to each other or to a voltage rail of some sort. Additionally, If you have other JTAG compliant chips that happen to be connected to nets of another JTAG chip, you can easily confirm assertions not only from one parts perspective but also from others, all without the use of several hundred test points or more. Test points can take up a lot of board space as you know. All of this can be done for as little as 4 control points for the JTAG port interface itself. I would swear by this test methodology, and have used it succesfully several time now. My new CM wants to use it as well, they have several years of data now which proves that JTAG type testing can increase production reliability for very little board real estate. If your curious at this point somewhere on TIs web site they still have a really good and simple DOS based JTAG tutorial. It will run in a DOS shell under windows too.

good luck,

stelleb

 

[SteveSmith]

stelleb,

Thanks, you deserve a gold (well purple) star for this tidbit.

Regards, Steve Smith
Product Engineer
Staco Energy Products Co.

http://www.stacoenergy.com

 

[Warpdrive]

Everyone,

Thanks to stelleb for the insights on JTAG boundary scan testing. However, be advised that while JTAG boundary scan test equipment is highly useful it can become pricey. I'm receiving quotes starting at $15K and going up for the JTAG BST system I'm seeking to implement.

Stelleb is also correct about test points consuming PCB space. I recommended test points because my most common customer's field technicians do not wish to be burdened with reading and deciphering 100-800 bit wide registers. That exercise is reserved for the engineers and production, T&E technicians. The trade off comes with determining how many test points are necessary and whether or not a JTAG scan tester is available. Ultimately, whether test points are used depends on any long term servicing requirements.

Where JTAG testing excels is accessing signals that are buried inside a chip, or are otherwise inaccessible to probing on the PCB. Stelleb describes this nicely.

If JTAG testing is not feasible, one "de facto" method of placing test points is using the vias that PCB tools automatically set during trace routing. Though this tends to scatter the "test points" across the PCB, it still makes key signals accessible without significant PCB real estate penalty. A little silkscreen can label each key signal at the via/test point.

Glad we could help.

-- Warpdrive

 

[JohnW]

Does anyone have advice on how to predict the life of the SMT assembly - before thermally induced fatigue creates failures? I have been informed that this is a significant problem for longlife (>10 year) products.

 

[DRWeig]

Hi Steve,

One other quirk that doesn't show up in most reference material is the care you have to take with any surface mount connectors that might be expected to take an external vibration or cantilever load. A row of header pins, for example, will have enough mass that they can't be effectively soldered in the same pass as the much smaller components on the board. Often these larger parts must be hand-soldered after the fact or you'll get a cold joint and they'll break off easily when being assembled to their mating connector (or worse, after installation to a vibrating piece of equipment).

Best of luck with your work!

Kindest regards to all,

Old Dave