Is there anyone here that knows what kind of tolerances can be held on a PCB in production from the edge to the center of a hole on and from edge to edge of a board as well. I'm looking for the best case tolerance without adding significant cost.
The best bet is to ask this question of the board makers because they constantly upgrade their processes and so will know the latest facts. Once they tell you you can decide if you need to push them or can live with the standard.
It depends on what you call out on the PCB drawing. Tofflemire is correct in that routing is typically +/-.005. But their are other edge details that can be specified such as scoring. It really depends on the volume and your assembly processes.
Best Regards,
Heckler
Sr. Mechanical Engineer
SW2005 SP 5.0 & Pro/E 2001
Dell Precision 370
P4 3.6 GHz, 1GB RAM
XP Pro SP2.0
NVIDIA Quadro FX 1400
o
_`\(,_
(_)/ (_)
Never argue with an idiot. They'll bring you down to their level and beat you with experience every time.
noslo21-
I can give you pattern-locating and in-pattern positonal tolerance on holes in GD&T terms. Would that help?
The problem I've always encountered is the PCB designers don't understand GD&T and/or their drafting software does not have provisions for showing the symbols. Of course most are either disinterested or too busy to learn something that seems inconsequental to them when they've used RFS bilateral dimensioning "all these years without any problems" (although IPC preaches the stuff)!
I did a survey once with ten major PCB mfgrs and they understood GD&T and provided (after much cajoling and coaxing to speak the TRUTH instead of CYA) fairly consistent data. I'll share the data but can not provide the sources.
I would be very interested in this data. I have no problems geometric dimensioning and tolerancing. As a matter of fact, I wish that more companies would adopt this as a sole method of dimensioning their drawings. It just solves to many problems (assuming that a supplier can understand it) with ease.