RF power amp that can withstand infinite VSWR 2

[Renovator1]

Hey all. I got roped into building an RF power amplifier for a physics professor friend and I wanted some second opinions on which way to go with the design. The amplifier needs to deliver up to 300Vpp and 100W across the frequency range of 0.1 to 1 MHz into a purely capacitive load (~200-1000pF), preferably without tuning...

Much as I'd like to, I don't believe I can get away with whipping up a quick-and-dirty push-pull Class B out of some spare SMPS parts. It seems like I've only got two choices here, but I'd love to hear otherwise:

1) Single-ended Class A (with either a choke or a cascode current source feeding the drain to at least get 25% eff.)

2) high-speed current feedback op-amp driving a FET voltage gain stage then a FET current gain stage (ala EDN's Design Ideas from April 26, 2001).

The distortion requirement isn't too critical, so that's a plus, at least. Any ideas or comments would be most welcome.

-Jeff

 

[sreid]

 

[sreid]

Alright, I posted a schematic above.

The opamp provides the gain for the amplifier. R1 sets the bandwidth; make it bigger until you get the bandwith you want. C1 makes the gain (20, 1k input res and 20k feedback res) exact.

The PNP level shifts the signal to the negative power rail.

The NPN level shifts the signal to the Gate drivers.

The key to this circuit is the +/-15VDC that floats on the amplifier output. It is a DC bootstrap and also supplies power to the HA5005 power buffer gate drivers. The zener sets the gate voltages to just below conducting.

 

[Warpspeed]

o/k Warpspeed almost completely incapacitated by a Linux operating system (with no CAD schematic drawing ability as yet), over eating, too much Christmas cheer, and probably latent alcohol poisoning, is about to have a go at this.

A video speed amplifier capable of a couple of volts output is ac coupled to a 1:1:1 pulse transformer. This amplifier has total dc feedback, and has the inverting input ac tied to a current shunt in series with the capacitive load.

At each end of this, is a voltage to current converter consisting of a bipolar transistor and suitable emitter resistor. This will be held approximately in class AB by the biasing diodes in the series string. This series string could also provide power to the op amp.

Both these voltage to current converters drive one or more common gate mosfets in cascode, providing a constant current high impedance drain output current to drive the load.

Warpspeed is not feeling his best right now, but offers this as a Christmas suggestion, but will probably regret it later, once completely recovered from the after effects of Christmas.

 

[Renovator1]

Thanks for taking the time to sketch out schematics, sreid and Warpspeed. I do appreciate it, even though, yes, Warpspeed, your circuit looks about as stable as a sailor on shore leave at 3:00am... I've only given them a cursory analysis so far but I will say they both have some interesting pluses and minuses. I do have a couple of quick questions for you both, of course.

sreid - Your design requires a conventional (i.e. - voltage feedback) op-amp such as the EL5100, to be stable, correct? Also, directly driving the base of the PNP (no base resistor with speedup capacitor, Baker clamp, etc.) as well as it being in common collector mode seems to be about as slow as is electronically possible... Finally, I want to confirm that the collector of the NPN connects to the floating 15V supply.

Warpspeed - I really like the use of a pulse transformer here, but I'm not sure if the phase lag from it will cancel out any of the phase lead from driving a capacitive load when the feedback signal is the load current. This is otherwise fairly similar to the op-amp based design I was contemplating.

 

[sreid]

The opamp is voltage feedback. It has to be fast but I can't tell you how fast. The opamp is not the only gain block so it's output does not swing all that much. The primary gain is at the output FETs. A gate to source voltage swing of one volt may cause the output to swing 150 volts.

The trick to stability is to minimize phase shifts everywhere. The PNP is actually pretty fast since it has a gain of 1/2 which means there is little Miller capacitance slow down. The NPN level shifter has a bigger problem since small changes in collector current cause big voltage changes. So the NPN needs to be fast. This part of the circuit may have to be changed to a cascode.

The collector of the NPN is tied to the zener as shown.

There are tens of thousands of this circuit in the field working at +/-50V, +/-10A at 300 kHz driving an LR load (servo motor).

 

[Renovator1]

That the circuit is already in use tends to nullify a lot of the "that can't work" arguments one may be tempted to make, eh?

Ok - after thinking about it I see my mistake concerning the PNP - it's a voltage controlled current source. E.g - let's say the op-amp output is +10.6V. This will cause 1mA to flow through the PNP's collector which will develop 5V across its 5k load resistor. It is at this point though that my analysis falters as there seems to be no DC pathway from the +15F supply to the -150v supply that the NPN emitter is referred to unless the lower (p-ch) FET is turned on. Mind you, I do feel like I might be missing something obvious here, so take all the joyful glee you deserve in pointing it out if I have

I agree that a Cascode instead of the lone NPN is likely necessary for 1MHz of bandwidth. What is the Ccb on the NPN you are using for the 100Vpp/300kHz driver now?

 

[Warpspeed]

Stability and phase shift is certainly a concern at 10 Mhz, but the pulse transformer should be the least of your worries. A very small toroid with trifilar windings would be ideal. All three windings have one end virtually held at ac ground, so there will be no excessively high ac common mode voltages between windings to cause problems. These broadband transformers are fairly easy to apply, and work very well at isolating high dc voltages with tightly coupled trifilar windings. The primary and secondaries will probably need some suitable terminating resistors to set the operating impedance, and damp any ringing. A video or broadband RF amplifier should be capable of driving such an impedance with minimal phase shift, and to the required low amplitude.

On further reflection, My main concerns with the above circuit would be the bipolar transistors, and stabilizing the dc bias operating point. It is really just an initial concept circuit and definitely needs some further detailed development. But at least, that is how I would probably begin.

 

[Renovator1]

Warpspeed - Yeah, it ought to be better to connect the pulse transformer secondaries to the FETs instead of the bipolars and, instead, bias the bipolars to follow Vgs plus a few volts. Also, power dissipation in the dropping resistors for the op-amp supply zeners could be considerable, depending on how much drive current the op-amp actually needs to supply. Heck, even at an average output of 10mA you're already over a watt in Pd for each zener. This is a relatively easy problem to solve, though - just buffer each zener with the appropriate polarity emitter follower.

I do a lot of high power (>500W) SMPS design and at these power levels one rarely exceeds a switching frequency of 300kHz because of parasitics and strays. Hence, my unfamiliarity/trepidation with attempting to deliver even a modest amount of power at up to 1MHz. Frankly, this is not my strong point (I guess if it were I wouldn't be asking for help here, huh?). So, thanks again for your comments and patience (even though I hope this provides some entertainment value as well, if for nothing else than the 'chuckle factor'...

 

[Warpspeed]

The problem with driving the fet gates directly will be that you will be fighting Miller capacitance, as well as the high gate/source capacitance. You will need MASSIVE gate drive power, but it may still be feasible or even preferable to do it that way??

A brick type RF power amp module could drive a broadband transformer, and run the whole thing open loop without any direct feedback at all. Just use some sort of AGC system around the whole thing to control the output amplitude.

Using a grounded gate cascode output stage vastly reduces the Miller problem, and the required drive power. You just need a suitable voltage to current source in the mosfet source. Maybe even another mosfet? Or how about a whole bunch of small jfets in parallel? They would need to carry around an amp, but the voltage is low. Jfets make excellent high frequency current sources, and they are readily available in both N and P sexes. Finding suitable bipolars with enough high frequency gain to work well, may be problematic.

The op amp can obviously be powered separately, but I do not see high resistor power dissipation as a disadvantage. Those gold metal clad resistors are excellent for this type of application. The output mosfets are going to get pretty hot anyway, a few extra watts of uselessly wasted power will not be noticed.

 

[Renovator1]

Yeah, you certainly do need massive drive power capability if you insist on hard-switching huge and/or older generation MOSFETs and IGBTs at high dv/dt. Quasi-resonant switching and/or using low total gate charge MOSFETs (such as the IXTH22N50P sreid uses) have greatly relaxed what was becoming a ridiculous problem for the industry.

The basic push-pull (Class A or B) RF power amp design was what I figured I could get away with in the first place. The amplitude does need to be held fairly constant: <1% would be ideal; 5% would probably be fine. That said, they are currently driving the funnel open loop with a general purpose function generator and a very pricey ENI AP400B 400W laboratory wideband amplifier. The single-ended output is converted into push-pull with a custom transformer I whipped up out of some junk box parts (it replaced one *they* had whipped up out of junk box parts, except they used the wrong core material, poor winding technique, had no concept of skin effect, etc.., and therefore their transformer always started smoking within 30s of being powered up).

At any rate, the op-amp based circuits are easy to control amplitude with; for the more basic push-pull RF amp topology do you all think that AGC or a smidgen of negative feedback (e.g. - a shunt R-L-C network from drain to gate) would be easier to implement? I keep reading that negative feedback is tricky to use in RF power amplifiers, yet I've seen it in plenty of circuits designed by amateur radio folks (usually over the 2-30MHz range).

I dream of getting the best of both the RF and audio worlds bere by using a high output current op-amp as the input stage of a basic transformer-coupled push-pull amplifier. Unfortunately for me, I suspect, this setup may be nigh impossible to stabilize (feedback after two transformers in series and a capacitive output load... sounds more like a power *oscillator* than an *amplifier*, doesn't it?)

 

[sreid]

I don't remember what NPN transistor I used and I don't have a schematic at home. Since we both have seen that a cascode is probably needed here (3x the freq and 3x the voltage) some other type may be required. I did use TO220 packages for both the NPN and the PNP as there is a fair amount of power dissipation in both devices.

It is difficult to see the current path for the floating gate drive circuit. The return path is the source connection of the output FETs. It may be easier to visulize if one biases the FETs class AB and connect the output to a load resistor.

A note on the output FET gate drive current requirement. Both FETs are used as Source Followers operated in the linear region, the primary drive current requirement is charging / discharging the gate capacitance. The P channel FET has an input capacitance of 10,000 pF. At 1 MHz this is 16 Ohms. But the gate drive excursion is perhaps
2 V p-p. So

Irms = Vrms/R = 0.7/16 = 50 ma (RMS)

a current that the HA5005 power buffers can easily supply.

 

[Warpspeed]

Overall negative feedback would be a very nice feature to have, but perhaps feedback around just the output power stage may be all that is required.

The power output stage absolutely must be a very high impedance current source to charge/discharge a capacitor. Any voltage feedback would lower the output impedance and be self defeating. It is the current passing through the load that needs to be controlled, driven, measured, and fed back. This should be possible over the required 10:1 frequency range with very low phase error and distortion if the voltage to current conversion is carried out properly.

Now for another completely different line of thinking.....

Would it suit your application to tune the load to resonance with a stepper motor driven roller inductor, and perhaps some switched lumped inductance? That would solve a whole raft of problems and be far more power efficient.

Automatic antenna tuners do precisely this, and have been successfully home built by many radio amateurs. It is just a case of bringing the voltage and current into exact phase and perhaps also to a required impedance, by having a simple microcontroller do the appropriate things.

 

[Renovator1]

Warpspeed - I agree that the output current must be controlled for the best stability when driving reactive loads, but for this application the output amplitude is critical as it determines the magnitude of the e-field produced in the ion guide (the ion guide is very much like the electrostatic deflection plates in CRT scopes). In fact, amplitude must increase with frequency here.

I also agree that a lot of design problems could be sidestepped if any sort of "antenna matching" were employed. I'm saving that for if/when all else fails, though, as it either greatly increases the complexity of the overall design or requires manual intervention on the part of the operator (e.g. - the grad students running the experiments...).

sreid - I believe I understand now how your circuit works but SPICE (TINA DesignSuite v7) doesn't seem to. The output is a distorted sine wave with a -100V DC offset. Of course, it is crap like this that reminds me why I almost never simulate a circuit in SPICE...

 

[Warpspeed]

There are really two separate problems here. Driving the capacitive load, which will be quite a challenge all by itself, and then very closely controlling the output voltage amplitude.

The amplitude control problem is really a case of adjusting the drive level to the power stage to reach the desired output voltage. Direct true negative voltage feedback is not really feasible, and not really necessary. It probably will not control the output amplitude very well either, if amplitudes are drifting or uncertain elsewhere in the system.

Read the actual peak output voltage with a fast peak reading rectifier, and then use a gain controlled amplifier stage to adjust and correct the amplitude. It is sure to produce the most dependable final result, independent of time, temperature or operating frequency.

 

[Renovator1]

I've spent a good chunk of the last couple of days simulating several circuit variations in SPICE despite my not being a big fan of it. That said, TINA v7 at least earned some confidence from me because the various amplifiers often broke out into oscillation when I tried to close the loop - which is pretty much what I would have expected. There is at least one nice thing about SPICE that I've noticed - you don't get a face-full of exploding FETs when a power amplifier turns into a power oscillator...

sreid - your circuit does appear to be one of those that SPICE says will never work but which in real life works just fine (it's certainly simple enough to go ahead an build one regardless). This, anyway, is preferable to the kind of circuit SPICE says will work just fine but ends up as a total disaster when actually built.

 

[Renovator1]

sreid - I found out why your circuit doesn't work in SPICE... Apparently, very few op-amp SPICE models account for quiescent and/or dynamic current through the supply pins; ergo, there is no DC pathway. Looks like I'll have to use "MSPICE"* to see if it works or not

* - Manual SPICE; i.e. - quite screwin' around with a mouse and breadboard the damn thing!

 

[Warpspeed]

You will also need to account for the finite capacitance to ground of the floating +/- 15v supplies. That will need to be driven to possibly over +/- 100v at 10 Mhz.

Do you think the driver stage with a source impedance of around 10K will be up to the job?

 

[Renovator1]

sreid - On a whim I substituted HA-5002 buffers for the floating gate drivers and lo-n-behold, now your circuit produces more or less reasonable results. Go figure...

That said, the NPN driver is, as expected, the Achilles Heel here (as evidenced by the op-amp output starting to go rectangular around 230kHz). But there is no evidence of instability all the way up to 1MHz so it looks like only straightforward tweaking will be needed to get the speed up (e.g. - changing the collector and emitter resistors for the NPN to 3k and 1.5k, respectively, boosted the upper limit to ~ 400kHz).

Warpspeed - I'd like you to revisit your circuit now that you have (presumably) recovered from the holiday excesses. Attached is a picture showing the schematic as I re-drew it with what I felt were reasonable component values. Your circuit as drawn only produces a 90V DC output within 5uS of startup.

The output impedance of the NPN driver in sreid's circuit is 3.33k, not 10k, and the max. freq. I need to deliver is 1MHz, but I think I get your point. That said, I don't see the problem as long as there is good (read: local) bypassing of the buffer supply pins...

 

[Renovator1]

Ignore the file uploaded in the previous post - it had a few errors in it. I corrected those and have uploaded the new schematic to the link below...

This one outputs a signal riding on top of a 90Vdc offset and has serious convergence issues when attempting transient analysis. Once again, I am not a big fan of SPICE so I don't use it that often (and has already been illustrated, I am not immune to 'operator error').

 

[Warpspeed]

Nice schematic drawing job, thanks Renovator.

Ha-ha, all through this I have been thinking 1Mhz to 10 Mhz frequency range. I should have gone back and read your first post more carefully.

Your main objection to my design seems to be the 1:1:1 coupling transformer. If this was just a "normal" Faraday type voltage transformer I would most certainly agree with that objection.

Correctly terminated broadband transmission line transformers are fundamentally very different in operation. If you are completely unfamiliar with these things, a little reading may open up a whole lot of new possibilities.

Usually the windings of broadband transmission line transformers all operate at a common dc voltage, but there is no practical reason why they must. They can offer high dc isolation without losing any of their excellent high frequency (and phase) broad band characteristics.

The two great pioneers in this field were Guanella and Ruthroff, and there is an excellent book available containing a wealth of practical hands on design information.

http://www.highfrequencyelectronics.com/Archives/Feb04/HFE0204_Sevick.pdf

http://www.frenning.dk/OZ1PIF_HOMEPAGE/AN749.pdf

http://www.amazon.com/Transmission-Line-Transformers-Jerry-Sevick/dp/1884932185

- 201k

Google will turn up vastly more.