SMPS with 0.01% ripple

[zxt50]

I am trying to design a 10KV (Vout) SMPS with 1V peak to peak ripple on the output voltage. (No linear regulators are allowed here).

The load is a pulsed load and could be anything up to 250Kohms. The load duty cycle is 10% or less. And the Pulse repitition frequency is 200Hz to some 30KHz.

The SMPS will have a switching frequency of around 15KHz and will be of the 4 transistor bridge LLC resonant converter type.

First of all, does anybody believe that this low ripple is possible (i.e. 0.01% ?)
Also, if not possible, what do you believe is the lowest amount of ripple that can be achieved?

Also, do you believe that analog PWM IC’s will be best, or will one of the new programmable (DSP) PWM controllers with on-chip ADC’s be better for this kind of regulation?
(I know of one such IC which has a 500ns ADC read time (2MSPS).)

 

[itsmoked]

Naw no 0.001 or 0.01 nor 0.1 for you...

I'll put my money on 1%.

Remember a switcher needs ripple.. That's what it controls with. No ripple.. Bad things happen.

You might as well give the dsPIC a try. The one for switchers. You should probably get the dev board and start hacking.

Keith Cress
Flamin Systems, Inc.-

http://www.flaminsystems.com

 

[benta]

Keith, why would a switcher need ripple?
I agree if it's a self-oscillating type, but who'd design such a thing today with all the excellent control chips available.

Anyway, 0.01% is far off the mark, I would even hope to be able to do that with a linear regulator.
As it seems pulsating loads are involved, the transient response issues wouls be enormous. I'm not certain whether the OP also calls this "ripple".

Benta.

 

[zxt50]

Hi,

Thanks for these replies.

I am including the transient response situation in the ripple. The load is switching and it's not possible to tell exactly what the load will be when it switches on, the SMPS will just have to regulate well and keep the ripple down to 0.01%.

Apologies...in my original post, -i meant that 250K was Maximum Load.

I tend to agree that switchers need ripple. In fact an open loop SMPS with a fixed load would even have ripple, due to the fact that SMPS's kind of pulse energy to the output. In fact, this ripple seen in such an open-loop case would be the best case ripple achievable with that SMPS, if it later became regulated with variable load.

 

[Warpspeed]

Interesting problem.

There is always going to be some conflict between stability and response of the switcher, and a massively over filtered output.

My approach would be a very large output capacitor with suitably low Esr. If it is a pulse rated capacitor as used for high energy discharge applications, it will, by design, have a very low series resistance and inductance.

To achieve suitably low output ripple it will probably require some fairly significant series impedance between the switching power supply, and this output reservoir capacitor.

The trick is how to best arrange dc feedback to control the switching supply, so that it regulates reasonably well, and remains stable.

I have had success taking direct dc feedback right at the load point, but ac coupling the feedback direct from the rectified dc output from the switching supply. This ac coupling bypasses any inconvenient phase lag in the output filter components, but dc feedback is still sensed right at the load.

I am sure with a bit of fiddling this will work for you, it may even require two smaller stages of filtering at the output. A lot depends on the exact nature of the load variations.

 

[BobbyNewmark]

How about an isolated linear section to "top off" the output?

Power it with an isolation transformer, give it a -15 to +15 V output range controlled by an optocoupler, and put it in series with the switcher output.

And give it really good transient protection.

 

[Madcow]

You may want to look into multi-phase switching for ripple cancelation.

 

[DHambley]

I've designed high-voltage TWT supplies before with similar specs. These type of supplies typically require 0.01% ripple so the answer to your first question is, yes, 0.01% is possible. I'd suggest a current fed controller using CMC with a damped response so that the voltage doesn't O/V between the load pulses. The design is all about noise control and calculating your capacitor parameters. (assuming you know how to design for high voltage) Analog PWM is the way to go. DSP is going to yeild too much bit error, but, this is the least of your challange.

 

[logbook]

A switcher does not need output ripple! now if you use a PWM switcher there will be a finite ripple rejection of the input ripple. However, if you use a current mode switcher the primary ripple rejection will be excellent. Rejection of output load ripple is a whole other matter. First you use a large output capacitor for the fast stuff. then you use a high frequency switching frequency so the loop can respond quickly.

 

[zxt50]

Thanks for these contributions.

"use a high frequency switching frequency so the loop can respond quickly. "

Regarding the above, kindly received from Logbook, I believe you are right, -however, there is some thought now that we want a low SMPS transistor switching frequency....this is to reduce switching losses and keep the switching transistors as cool as we possibly can.

But i can see that this low frequency switching is entirely in opposition to our wish to have low output ripple. So this is a sticking point.

 

[BobbyNewmark]

The frequency issue is why somebody suggested a multi-phase approach. Use several lower-frequency switchers in parallel, run them off the same clock, and stagger their switching times. If there are N sections running at frequency F, then the load will see ripple at frequency N*F. Furthermore, the current per section is reduced by 1/N, making for smaller transistors and inductors. Because of the higher frequency, the input and output filter capacitors can be shrunk.

For example, use four phases at 15 kHz, and stagger them so they switch ~67 microseconds apart (90 degrees of phase). That feeds power pulses to the load at 60 kHz.

 

[logbook]

Well now we have two sorts of ripple. Primary ripple rejection and secondary load rejection.

Primary ripple rejection can be made arbitrarily low by filtering the input and using a current mode controller. The resulting increase in cost and reduced efficiency has to be considered.

Secondary load rejection is improved by
a) faster loop response
b) secondary regulator
c) feedforward load compensation

We have discussed a and b so far.

If you know a load is about to switch you can "unswitch" another load or boost the primary power. This is an open loop correction but if adjusted suitably will probably reduce the ripple by a factor of at least 5x. If the load is arbitrary and uncontrollable then this method will not work.

 

[zxt50]

hgldr, thankyou for your response regarding SMPS design for low output ripple...


"Analog PWM is the way to go. DSP is going to yeild too much bit error"

With reference to this, with dsPIC30F2020, i can get 10 bit resolution for feedback voltage with the on-chip ADC. Also, the sample rate is 2MSPS.....do you think this is going to badly affect my output ripple? (i.e. compared to analog PWM)

Also, with reference to the 0.01% ripple spec for output voltage.......would any reader know if this is possible using just one SMPS stage with "no extra bells & whistles"?...eg, no post-regulator, no extra filter.....just the basic topology with its secondary rectifier and LC filter (assuming its a 4 transistor bridge, say).

 

[DHambley]

The 10bit resolution of the PIC DSP gets you in the ballpark of 0.1% but my concern with digital control is that most control loops need a zero for stablilty. The Z-domain equations will show this requires calculating the difference of various samples. The resolution is only +/- one bit. This usually results in the final output dithering back and forth by a few bit-weights. It's very stable, but it has to jump up and down a few bits.

 

[MacGyverS2000]

Also, getting 10 bits of accurate resolution from a clean system on a PIC can be a bit challenging (though quite doable), but add in a noisy motor and you might as well consider it an 8-bit system without some serious thought on circuit design and layout.

Dan - Owner

http://www.Hi-TecDesigns.com