Transformer saturation in SMPS

[Tyranosaurus]

Push-pull or H-Bridge converter in voltage mode control may suffer from xfmr saturation. H-bridge can use a DC-blocking cap to eliminate xfmr saturation. However at low source voltage and high current that is expensive. Are there better ways to assure non-saturation? Maybe via current sensing? But how does that affect the operation of the H-bridge? Noise? chaos?

 

[Skogsgurra]

It is usually done by designing the core and the windings to accomodate the necessary Vs area. Trying to squeeze more than that out of the transformer may be possible with some sort of a saturation detecting scheme and letting the output from that control pulse width. But sounds more complicated than needed. And not very reliable either.


Gunnar Englund

http://www.gke.org

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100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...

 

[Tyranosaurus]

If the two halves cyles don't have the same volt-second - which normally is the case - over time that will lead to xfmr saturation, so that oversizing the xfmr would not work? I've read about schemes for compensating xfmr saturation a long while back. I guess using a mix of CMC and VMC could work, without the trouble of slope compensation. What bugs me is the prototype doesn't seem to saturate without any current sensing for now. Any reference welcome. My old Unitrode seminar book doesn't suggest a definite solution.

Thanks for the reply anyway. I'll keep searching.

 

[Skogsgurra]

DC components in the waveform is, of course, not good. But that should be attacked on the control side, I think. By making the positive and negative areas equal. That is either a question of sensing the average value and keeping it at zero or simply putting restictions on the + and - timing. Desperate solutions include a capacitor in series with the primary.

Gunnar Englund

http://www.gke.org

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100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...

 

[Madcow]

Gap the core. Make shure the switches have similar charactoristics and drive delays. Check the layout.
Should be symetrical. I've had the Drain source cap.
increase significantly on an h-bridge do to traces
sitting on top of each other. Also you can increase
your dead time. Noise can also cause inbalances.
Make shure the CT(osc. cap.) is as close to the pins
as posible and leads as short as posible. Most manufacturers
put the ct and rtn next to each other.
These should help, but current mode is probably the best.

Searh on FLUX WALKING TRANSFORMERS. I got a lot of hits.

 

[cbarn24050]

Hi, your drive waveforms should be identical since most controllers use a flip flop. You should have some dead time to protect your power transistors, this dead time will allow the core to reset any minute imbalance. Most controllers have current pulse limiting which cures the problem anyway.

 

[DHambley]

"the prototype doesn't seem to saturate without any current sensing for now"
This may be due to your protoype having an even load (simple resistive load maybe) and large filtering of the pulse-width (combined with voltage-mode control) so that it doesn't change rapidly. If the pos & neg PW's are about the same, a steady offset of the BH curve will result (and it'll get as big as it needs to be) so that the offset current multiplied by the impedances will correct any small imbalances of your driver.

 

[Tyranosaurus]

Load current has nothing to do with xfmr saturation. It's the volt-second imbalance cause by any dissymetry, D or Rds,on. Proto works but I want reliable design by anticipate potential problems. Current sensing and turning off the active switch at excessive current is probably the best way I know. Thx for all posts. What bugs me is IEEE's power electronics publishers almost never mention this problem in their papers. Granted they're used to hiding things.