Voltage Spikes in Integrator CKT 2

[hevykevy]

Hello all,

I am having a small problem with a square-wave driven integrator circuit. The details are as follows:

Input voltage: +/- 2.5 V square wave at 24kHz 50% DC
Feedback Cap: 4700pF
Input Resistor: 2.55k
Configuration: Inverting
Power Rails: +/- 2.5 V
Desired output: 24kHz triangle wave

The integrator produces a nice triangle wave for the most part, but there exists a voltage spike at the peaks of the output (when the input changes polarity) on the order or 700mV in amplitude. I have experimented with different op amps and not surprisingly found that the amplitude and duration of the spike are directly related to slew rate (faster SR producing higher amplitude spike for shorter time duration and vice versa). I was wondering if anyone could give me a better idea as to why this spike is occurring. What non-idealities of the op amp create this spike? How can I choose an op amp to limit this spike?

My main concern regarding the spike is that it may harm components down stream if used as the input. I believe the op amp chosen is capable of rail-to-rail inputs and outputs, yet the spike may exceed the rail voltage. Besides using a LPF, how can I limit/rid the spike?

Any ideas?

Thanks,

Kevin

 

[cbarn24050]

Hi, that shouldn't happen, it's probably noise from the squarewave generator, try some power supply decoupling near each ic.

 

[nbucska]

ake sure that the inv. input is properly decoupled and located so that it can't pick up noise.

Is the spike the same polarity as the triangle ( pos. on
the positive peak ) measured on the op.amp output ?


<nbucska@pcperipherals.com>

 

[Heydave]

It comes from the type of output stage amplifier circuit in the op amp. When polarity changes, one set of drivers switches off and the complement switches on. The design of the op amp determines how well this is done. Any overlap results in a short across the opamp power supplies so instead, there is designed in slight gap. The load characteristics on the output effect what this gap looks like. If you want to eliminate it, be prepared to waste some power. High slew rate comes from turning on transistors harder but that means a greater chance of overlap so design tradeoffs are made. Improve your power supply bypassing to get the best performance and possibly look into some series resistance on the output to reduce effects of capacitance and inductance in the load.

 

[nbucska]

You may slow down the square wave to get the best compromise.

<nbucska@pcperipherals.com>

 

[Comcokid]

You have to watch your layout carefully on integrators. Example - If you have two parallel traces - one on your integrator and the other with your square-wave signal, just this little amount of coupling is enough to add a hump in your integrator.

Remember, the feedback on an op-amp integrator is via a capacitor - effectively a very high impedance at low frequencies and infinite impedance at DC.

 

[BrianG]

Following on from Comcokid's post, you could try a high-ish value resistor in parallel with the capacitor to reduce the d.c. gain of the op-amp. The op-amp gain needs to be kept resonably high otherwise the ramp from the integrator will start to distort. For starters try 220K, which should give you a gain of about 100, and see what happens.

 

[nbucska]

Briang is right, it is good to limit the DC gain -- if
acceptable -- but it has nothing to do with the spike.

Kevin : Waiting for the polarity of spike .

<nbucska@pcperipherals.com>

 

[hevykevy]

nbucska, the polarity of the spike is the same as the polarity of the output waveform. Therefore, the spike adds to the peak to peak value of the entire waveform.

 

[nbucska]

The input: _-_- when inp. is + output goes down
The output /\/\

The rising edge causes a positive spike i.e. the SQW input
has capacitive xtalk to the non-inv, input. Add GOOD decoupling, rearrange the circuit to reduce the distance or move parts to the other side of the board, add shield etc.

If the op.amp is fast enough, you may try to add a SMALL
cap parallel to the 2.55K input R in series with the small
R.


<nbucska@pcperipherals.com>

 

[logbook]

There is some misleading information here as to order of magnitude of effects. The triangle wave you expect/get is around ±2V. The spike is ±700mV, taking the output almost up to the power rails.

First let’s look at BrianG’s comment about adding a resistor across the capacitor. This is not a "nice to have", it is an essential. The integrator has infinite gain to the DC component of the waveform, and to its own offset, if no resistor is used. There is no evidence of your using a reset circuit anywhere, so the opamp will hit the power rails, one way or the other, unless you define its DC position somehow. This, however, is nothing to do with the spike, as nbucska correctly observes.

Next let’s look at the spikes. People are talking about common-mode rejection problems and cross-talk. In order to get 700mV spikes on the output you would have to have 700mV spikes on the non-inverting input. That is not cross-talk or power supply rejection, that is a complete disaster! You have a definite gross fault in your circuit. You say that you have ±2.5V rails, suggesting that the positive (non-inverting) input of the opamp is sitting at ground (0V). I don’t believe you

Measure things in the area with a scope probe, particularly the so-called grounds. We are not talking about the sub-mV levels people normally worry about for cross-talk issues, we are talking about 700mV! I suspect that the ground is being generated by a virtual ground generator, or some such thing, and what you thought was ground really isn’t. Either that or you are using a <10ns square wave edge and didn’t mention it.

 

[nbucska]

A star to Log for taking the time to calculate !
The OP.amp may be too fast, too, or the 4700pF may have LONG
wire in series ??

Try to slow down the _-_-


<nbucska@pcperipherals.com>

 

[hevykevy]

A few things I need to clear up:

1.) The circuit is being generated on PSPICE, and is not built at the moment. All problems are being reported from P-SPICE, and not live data.

2.) Don't worry about the DC drift it is taken care of and like many of you said, does not pertain to this problem.

3.) The non-inverting terminal is grounded with a series resistance of 2.55k ohms.

4.) If spikeless, the output of the waveform is approximately +/- 2V; therefore, the spikes cause the input to exceed rail voltage.

5.) During the simulation, you do see a small spike at the inverted input to the op amp when the square wave changes polarities, this small voltage spike is not seen on the grounded non-inverting terminal.

I hope this clears things up. I didn't mention the P-SPICE deal before as I am trying to put off blame of the software as a last resort.

 

[nbucska]

Something must be wrong with your op.amp model. Do not
use ideal _-_-

<nbucska@pcperipherals.com>

 

[hevykevy]

Notice my first post where I said that I dropped different op-amps in with slower slew rates and still saw the effect. So either all op amp models in PSPICE have this glitch, or it actually does exist in the real circuit.

The input rise time and fall times are on the order of 40 and 70 ns.

 

[cbarn24050]

You will find that you get better answers when you mention all the important facts, ie. garbage in garbage out. You should not have a spike on the inverting input. Post your circuit then we might get somewhere.

 

[logbook]

I get the same spikes on the SPICE simulator I use, SIMetrix, when using a TL072 macro model, but not when using an LF412 macro-model (I used ±12V rails). Some macro models are not very accurate representations of the real opamp. This is undoubtedly the problem you have.

Note that cross-talk, ground noise, ground loops etc are not modelled by SPICE based simulators unless you explicitly include components to produce these effects.