JeffJackson
Aerospace
Hi all,
Just wondered if anyone can recall the old fault code generated by Xilinx when mapping and fpga.
Using a XC4020HQ208, design simulates and compiles with no errors. When building I get NGDBUILD done then when mapping the following:
ERROR:OldMap:928 - There is no signal on pin A0 of CY4 symbol
This design ( as a previuos version) has built before OK.
I just needed to add a small change to a count, and now I can't build at all. Even using the previous version of my VHDL code I get the same error, I seem to have got a bug, that I can't kill. Any tips greatfully received.
Jeff
Just wondered if anyone can recall the old fault code generated by Xilinx when mapping and fpga.
Using a XC4020HQ208, design simulates and compiles with no errors. When building I get NGDBUILD done then when mapping the following:
ERROR:OldMap:928 - There is no signal on pin A0 of CY4 symbol
This design ( as a previuos version) has built before OK.
I just needed to add a small change to a count, and now I can't build at all. Even using the previous version of my VHDL code I get the same error, I seem to have got a bug, that I can't kill. Any tips greatfully received.
Jeff